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Thread starter loglong Start date Nov 29, Status Not open for further replies. It also goes through many revisions where new features are added and some older ones deprecated.
The reference manual for UVM can be obtained here and contains description on class hierarchy, functions and tasks. In order to make the last type of virtual sequences reusable at chip-level, it is better to plan ahead to abstract the data from the protocol. For example in Figure 1 of SoC diagram peripherals 1 through N are on peripheral bus which might be using a different protocol than the system bus.
There are two approaches to make the sequences reusable:. Use functional abstraction by defining functions in the virtual sequence that can be overridden like:. In this approach, a layering agent sits on top of a lower level agent and it forwards high-level transactions that can be translated by the low-level agent according to the bus standard.
The high-level agent can be connected to a different low-level agent without any change to the high-level sequences. A critical component of self-checking testbenches is the scoreboard that is responsible for checking data integrity from input to output. A scoreboard is a TLM component, care should be taken not activate on a cycle by cycle basis but rather at the transaction level.
A Scoreboard operation can be summarized in the following equations:. Sometimes the operation is described as predictor-comparator. Where the predictor computes the next output transfer function and the comparator checks the actual versus predicted compare function. Usually the transfer function is not static but can change depending on the configuration of the devices.
In SoC, most peripherals have memory-mapped registers that are used for configuration and status. These devices are usually called memory-mapped peripherals and they pose two challenges:. The common solution to the first one is to have a handle of the memory-map model and connect an analysis port from the configuration bus monitor to the scoreboard.
This approach has one disadvantage; each peripheral scoreboard has to implement the same functionality and needs to connect to the configuration bus monitor. A better approach is that the registerfile updates occur in a central component on the bus.
To eliminate the need for the connections to the bus monitor, the register package can have an analysis port on each registerfile model. Each Scoreboard can connect to this registerfile model internally without the need for external connections.
One of the requirements on the UVM register package is to have update notification method [6]. The second challenge is status bit verification. Status bits are usually modeled in the register model and register model can act as a predictor of the value of status bits. This requires that the scoreboard predicts changes to status bits, update the register models and on register reads the value read from the DUT is compared versus the register model.
At the SoC level, there are two approaches to organize scoreboards with End-to-End and Multi-step [2]. Figure 3 depicts the difference between the two. The multi-step approach has several advantages over the end-to-end:. These guidelines are not only for the methodology deployment but also for the verification process. This paper tried to summarize some of the pitfalls and tradeoffs and provide guidelines for successful SoC verification. The set of guidelines in this paper can help you plan ahead your SoC verification environment, avoid pitfalls and increase productivity.
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse. Stop-Interrupt Enabled Example.. Raising And Dropping Objections Example.. Raising And Dropping Multiple Objections Multiple Objections And forever-Loop Example.. Revision February - What Changed?
Figure 5 - run phase execution flow diagram without timeouts.. Figure 8 - Verilog style testbench Figure 14 - run phase execution flow diagram with timeouts.. Figure 15 - test3 UVM reported output.. Figure 16 - 1 run phase - Active Stage and Stop-Interrupt Figure 17 - test4 UVM report output after Stop-request timeout.. Figure 18 - test5 UVM report output after Watchdog global timeout.. Figure 19 - test6 UVM report output after Watchdog global timeout..
Figure 20 - test7 UVM report output after Stop-request timeout.. Figure 21 - test8 UVM report output after Watchdog global timeout..
Figure 22 - test9 UVM report output after all objections were dropped.. Figure 23 - test10 UVM report output after all objections were dropped. Figure 24 - test11 UVM report output after all objections were dropped.. Figure 25 - test12 UVM report output after all objections were dropped and stop task completed.. Figure 26 - test13 UVM report output after all objections were dropped..
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